Electrical Limitations in Epitaxially Grown Kerfless Silicon Wafers for Solar Cells

Abstract

In this work a quantitative approach to assess the specific material related efficiency limits of epitaxially grown silicon wafers is demonstrated. Based on experimental results of injection dependent carrier lifetime images on these wafers the absolute losses of identified defects, namely decorated stacking faults, defects from inhomogeneous processing and underlying homogeneously distributed recombination centers, have been quantified and compared. The losses from decorated stacking faults have been determined as a function of their lateral density. The obtained loss diagrams allow for systematic material optimization.