A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX

Abstract

The transceiver power is reduced by 27% in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS.