A novel 6GHz/ 573µwatt/ 30ps Dynamic Comparator with complementary differential input in 65nm CMOS Technology

Abstract

In this paper, a novel high speed dynamic comparator is presented, which its delay time is decreased compared to conventional dynamic comparators. In the suggested comparator, a complementary differential pair is utilized. As a result, the delay time is reduced and the offset voltage is improved. Furthermore, the delay and power consumption has less sensitivity to the variations of the input common mode voltage level. In the reset phase, an NMOS switch is utilized between the differential outputs nodes to reduce the delay time. The equations related to the delay time and input referred offset voltage of the proposed structure are derived and the effective parameters to reduce them are identified. The post-layout simulation results in 65nm CMOS technology demonstrate that the clock frequency of the proposed dynamic comparator can be 6GHz while the delay time is 30ps. The power consumption is 573µW when the proposed comparator is supplied with 1.2V. Also, the occupied area is 86.1 µm2 (10.63µm*8.1µm).