Variability induced by Line edge roughness in silicon on thin box (SOTB) MOSFETs

Abstract

Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage's variations, especially for n-SOTB MOSFETs.