A design flow for inductively degenerated LNAs

Abstract

A design flow to explore the design parameters space of integrated inductively-degenerated low noise amplifiers (LNA), under the constraint of matched input impedance, is presented. It is based on standard circuit simulation tools and can be easily automated. The method is applied to the design of a 5.5 GHz 0.18 /spl mu/m CMOS LNA with minimum noise figure (NF) for a fixed bias current. The measured NF of 2.6 dB, with input reflection coefficient lower than -15 dB at 5 mA bias current, shows good agreement with simulations.