{"title":"The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter","authors":"Jen-Shiun Chiang, M. Chiang","doi":"10.1109/ISCAS.2000.857126","DOIUrl":null,"url":null,"abstract":"An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"22 1 1","pages":"443-446 vol.1"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2000.857126","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.