The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter

Jen-Shiun Chiang, M. Chiang
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引用次数: 5

Abstract

An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.
设计一种1.5 V、10位、10 M采样/s的低功耗流水线模数转换器
本文设计并实现了一种实验性的低压低功率流水线式模数转换器。通过使用开关运算放大器和动态比较器,有效地降低了功耗。该芯片采用0.35 /spl μ m CMOS工艺设计。核心区占地面积1450 /亩/平方米/倍/1100 /亩/平方米。HSPICE仿真结果表明,该设计的分辨率为10位;采样率为10 MHz;峰值SNDR为66 dB,供电电压为1.5 V时功耗为15 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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