A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array

Abstract

This paper presents a1Tb 4b/cell 3D-NAND-Flash memory on a 176-tier technology with a 14.7Gb/mm2 bit density. The die is organized using a 4-plane architecture for multiplane operations with a 16KB page size. The 1×4 plane architecture improves both program and read throughput, without increasing the die size. Periphery circuitry and page buffers are placed under the array using 5th-generation CMOS under array (CuA) technology. To improve random read performance, a faster read is provided with a read concurrency feature: allowing four independent multiplane page read addresses. The 4b/cell capability is reached using negative voltage for an expanded window in the negative region and a positive SRC bias, both of which aid in extended reliability. The programming operation is based on a 16–16 programming algorithm. The I/O transfer speed is 1600MT/s in ONFl4.2. The 3D-NAND Flash technology has improved significantly in its performance and reliability, enabling a design of a high density of 4b/cell (QLC) device.