A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC

Abstract

This paper presents a low power technique to solve the gain variation problem of the dynamic amplifiers in pipelined SAR ADCs. To detect and correct the gain variation of the dynamic amplifier across different process, voltage, and temperature (PVT) corners, an amplification path parallel to the dynamic amplifier is added as a reference for comparison of voltage gain. To achieve high PVT-robustness and power-efficiency, a two-stage passive amplification path is proposed as the reference path. Designed in 40 nm CMOS process, across different PVT corners the gain variation of the dynamic amplifier and the SNDR degradation of the ADC are less than ±1.1% and 1 dB, respectively. The extra circuits for the stabilization technique only consume 18% of the power consumption of the dynamic amplifier.