Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

P. Buffet, Joseph Natonio, R. Proctor, Yu H. Sun, Gulsun Yasar
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引用次数: 22

Abstract

Electrical rule checking is fundamental to achieve a good I/O cell placement. This paper presents the analysis techniques used to design a robust power-grid structure, the method used to make I/O cell placement guidelines, details of the I/O cell placement process and electrical checking algorithms.
使用区域阵列电网的ASIC设计中的I/O单元放置和检查方法
电气规则检查是实现良好I/O单元放置的基础。本文介绍了鲁棒电网结构设计的分析技术、I/O单元布置指南的制定方法、I/O单元布置过程的细节和电气检查算法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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