The Core Chip Design of Inter-Integrated Circuit in 40nm CMOS

Abstract

This paper designs an I2C (Inter-Integrated Circuit) interface module. The I2C interface module is used in all digital phase-locked loop (ADPLL). The front-end simulation frequency of the I2C interface module is 100MHz, and adopt the design of host input and output from the slave. The I2C interface module is based on 40nm COMS process and has a total of 55 output pins.