{"title":"PySyn: A Rapid Synthesis for Mixed-Signal Machine Learning Classification","authors":"Farid Kenarangi, Inna Partin-Vaisband","doi":"10.1109/MWSCAS47672.2021.9531745","DOIUrl":null,"url":null,"abstract":"Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"712-717"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531745","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.