SiOC CMP developed and implemented in 7nm and beyond

Abstract

In this study, new SiOC Chemical Mechanical Planarization (CMP) process is fully developed with the characterization of the blanket wafer selectivity, SiN loss on pattern wafer, within chip SiN uniformity, and topography of CMP house and device areas using Atomic-force microscopy (AFM), Transmission electron microscopy (TEM), high resolution profiler (HRP) and KLA-Aleris. Those results of SiN within-chip uniformity show one step process (only slurry A_bulk + SiN stop) with poor process window, which cannot meet 7nm MOL integration process requirement. And two steps process (Slurry A_bulk + Slurry B_SiN stop) with promising results, good SiN within-chip uniformity (< 2nm) and wide process overpolish margin.