A cascadable 200 GOPS motion estimation chip for HDTV applications

Abstract

A flexible block matching motion estimation chip is described with variable sized blocks between 8/spl times/8 and 32/spl times/32 pixels. Each chip performs block matching with a search area of /spl plusmn/15 vertically and horizontally for a block size of 32/spl times/32. For larger search areas devices can be cascaded. Besides full search, fast algorithms can be emulated. Sub-pel precision motion vectors can be calculated using a smaller search area or cascading devices. The chip will have a computational power of more than 200 GOPS and a die size of 170 mm/sup 2/ in an 0.5-/spl mu/m CMOS technology.