Value-driven Synthesis for Neural Network ASICs

Zhiyuan Yang, Ankur Srivastava
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引用次数: 2

Abstract

In order to enable low power and high performance evaluation of neural network (NN) applications, we investigate new design methodologies for synthesizing neural network ASICs (NN-ASICs). An NN-ASIC takes a trained NN and implements a chip with customized optimization. Knowing the NN topology and weights allows us to develop unique optimization schemes which are not available to regular ASICs. In this work, we investigate two types of value-driven optimized multipliers which exploit the knowledge of synaptic weights and we develop an algorithm to synthesize the multiplication of trained NNs using these special multipliers instead of general ones. The proposed method is evaluated using several Deep Neural Networks. Experimental results demonstrate that compared to traditional NNPs, our proposed NN-ASICs can achieve up to 6.5x and 55x improvement in performance and energy efficiency (i.e. inverse of Energy-Delay-Product), respectively.
神经网络专用集成电路的价值驱动综合
为了实现神经网络(NN)应用的低功耗和高性能评估,我们研究了合成神经网络asic (NN- asic)的新设计方法。神经网络专用集成电路(NN- asic)采用经过训练的神经网络,实现定制优化的芯片。了解神经网络拓扑和权重使我们能够开发出常规asic无法使用的独特优化方案。在这项工作中,我们研究了两种类型的值驱动优化乘数,它们利用突触权重的知识,我们开发了一种算法,使用这些特殊的乘数而不是一般的乘数来合成训练过的神经网络的乘法。用多个深度神经网络对该方法进行了评价。实验结果表明,与传统的NNPs相比,我们提出的nn - asic在性能和能效(即能量延迟积逆)方面分别提高了6.5倍和55倍。
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