E. Ronconi, N. Corna, S. Salgaro, F. Garzetti, N. Lusardi, L. Bucci, A. Geraci
{"title":"SoC-based Architecture for General Purpose Real-Time Histogram Computation","authors":"E. Ronconi, N. Corna, S. Salgaro, F. Garzetti, N. Lusardi, L. Bucci, A. Geraci","doi":"10.1109/NSS/MIC42677.2020.9508087","DOIUrl":null,"url":null,"abstract":"In this contribution we present a novel implementation of a firmware and software bundle for the computation of real-time histograms based on a System-on-Chip (SoC) Linux-based platform. Histograms are basic instruments that turn out to be of fundamental help when it comes not only to single-shot events, but also to collection and elaboration of big amount of data, their shaping and statistical insights coming from the collected measures. Industry and Academia have already proposed many solutions to this need, both in full-custom Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) IP-Cores. However, despite being mostly satisfying in performance, these solutions often lack ease of use, upgrade and interfacing. Moreover, in this particular application, large storage capabilities are needed, in order to guarantee the user the possibility to build large enough histograms. To solve these issues, we present a hybrid hardware and software implementation of a Histogram Maker in an FPGA-based SoC. Its main features are the large available memory accessible through a Direct Memory Access (DMA), the low amount of consumed FPGA resources of the actual hardware Histogram (Histo-Pack), the real-time behavior and the simplified, yet efficient, interface to the ARM core in the Xilinx SoC, hosting a Linux-based Operating System. A set of IP-Cores and libraries relaxes the effort for the interfacing between the two worlds, so that the user-friendly Processing System can be connected to the programmable logic part to exploit its high-performance in an easy and flexible way. The system has been successfully validated on Xilinx Zynq-7000 and Zynq UltraScale+ devices. This opens new opportunities for simple data transfer through advanced interfaces and protocols, data elaboration and analysis, with no need for complex hardware on the Programmable Logic part. The system is able to receive up to 0.3 Gsps with a refresh rate of 1ms.","PeriodicalId":6760,"journal":{"name":"2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)","volume":"93 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSS/MIC42677.2020.9508087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this contribution we present a novel implementation of a firmware and software bundle for the computation of real-time histograms based on a System-on-Chip (SoC) Linux-based platform. Histograms are basic instruments that turn out to be of fundamental help when it comes not only to single-shot events, but also to collection and elaboration of big amount of data, their shaping and statistical insights coming from the collected measures. Industry and Academia have already proposed many solutions to this need, both in full-custom Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) IP-Cores. However, despite being mostly satisfying in performance, these solutions often lack ease of use, upgrade and interfacing. Moreover, in this particular application, large storage capabilities are needed, in order to guarantee the user the possibility to build large enough histograms. To solve these issues, we present a hybrid hardware and software implementation of a Histogram Maker in an FPGA-based SoC. Its main features are the large available memory accessible through a Direct Memory Access (DMA), the low amount of consumed FPGA resources of the actual hardware Histogram (Histo-Pack), the real-time behavior and the simplified, yet efficient, interface to the ARM core in the Xilinx SoC, hosting a Linux-based Operating System. A set of IP-Cores and libraries relaxes the effort for the interfacing between the two worlds, so that the user-friendly Processing System can be connected to the programmable logic part to exploit its high-performance in an easy and flexible way. The system has been successfully validated on Xilinx Zynq-7000 and Zynq UltraScale+ devices. This opens new opportunities for simple data transfer through advanced interfaces and protocols, data elaboration and analysis, with no need for complex hardware on the Programmable Logic part. The system is able to receive up to 0.3 Gsps with a refresh rate of 1ms.