T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai
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引用次数: 99
Abstract
This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for the deep sub-0.1 /spl mu/m era while maintaining the circuit speed. Applying boosted gate voltage on the low leakage switches with higher V/sub th/ and thicker T/sub ox/, extremely low stand-by power for battery type application is achieved, while degradation of circuit performance and an increase of area overhead are sufficiently suppressed. The combination with a negative gate voltage scheme and the application of the boosted voltage scheme to SRAMs are also discussed.