Sabyasachi Bhattacharyya, R. Sarma, K. Bhattacharyya, Ragib Nasir Ahmed, Roushan Saikia
{"title":"MUX-based design of DPLL for wireless communication","authors":"Sabyasachi Bhattacharyya, R. Sarma, K. Bhattacharyya, Ragib Nasir Ahmed, Roushan Saikia","doi":"10.1109/ICICES.2014.7033978","DOIUrl":null,"url":null,"abstract":"For modern day communication devices, the key aspect lies in the proper reception of data at minimum possible error rates and also on maintenance of great degrees of precision. But, while doing so, a very important aspect that should be kept in mind is the ability of the device developed to operate at reasonable speeds, because it must be compatible with the other sub-systems of the communication setup. Also, the design complexity of the device and the cost of design should be minimum. By putting all these factors together, we can define a common term called time complexity which is the main concern of this proposed work. Considering the various constraints at hand, we would like to propose the design of a Multiplexer-based DPLL device which comprises of features such as good speed, simplified design and precise reception of data.","PeriodicalId":13713,"journal":{"name":"International Conference on Information Communication and Embedded Systems (ICICES2014)","volume":"435 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Information Communication and Embedded Systems (ICICES2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICES.2014.7033978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
For modern day communication devices, the key aspect lies in the proper reception of data at minimum possible error rates and also on maintenance of great degrees of precision. But, while doing so, a very important aspect that should be kept in mind is the ability of the device developed to operate at reasonable speeds, because it must be compatible with the other sub-systems of the communication setup. Also, the design complexity of the device and the cost of design should be minimum. By putting all these factors together, we can define a common term called time complexity which is the main concern of this proposed work. Considering the various constraints at hand, we would like to propose the design of a Multiplexer-based DPLL device which comprises of features such as good speed, simplified design and precise reception of data.