A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-03-08 DOI:10.1109/ISSCC.2018.8310278

Daniel Weyer, M. B. Dayanik, Sunmin Jang, M. Flynn

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引用次数: 18

Abstract

Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-digital PLLs (ADPLLs) promise greater flexibility and area efficiency. However, existing mm-wave ADPLLs are large, fail to offer low in-band phase noise [1] or must rely on extensive calibration [2]. Performance limitations of conventional TDCs still remain a major roadblock for the adoption of high-frequency ADPLLs. To address this problem, this work introduces a noise-shaping TDC based on a 4th-order bandpass ΔΣ modulator (BPDSM) to achieve low integrated noise (183fsrms) and high linearity. Our approach enables low in-band phase noise (−85dBc/Hz @ 100kHz) for wide loop bandwidths (>1MHz) in a calibration-free single-loop digital 36.3-to-38.2GHz PLL. The prototype PLL effectively generates fast (500MHz/55μs) and precise (824kHzrms frequency error) triangular chirps for FMCW radar applications.

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36.3 ~ 38.2 ghz−216dBc/Hz2 40nm CMOS分数n FMCW啁啾合成器锁相环，带连续时间带通δ - σ时间-数字转换器

汽车雷达和其他毫米波应用需要提供快速沉降和低相位噪声的高质量频率合成器。模拟锁相环在毫米波范围内仍然占主导地位，但全数字锁相环(adpll)具有更大的灵活性和面积效率。然而，现有的毫米波adpll体积较大，不能提供低带内相位噪声[1]，或者必须依赖大量校准[2]。传统tdc的性能限制仍然是高频adpll采用的主要障碍。为了解决这个问题，本研究引入了一种基于四阶带通ΔΣ调制器(BPDSM)的噪声整形TDC，以实现低集成噪声(183fsrms)和高线性度。我们的方法在无需校准的36.3至38.2 ghz单环数字锁相环中实现宽环路带宽(>1MHz)的低带内相位噪声(- 85dBc/Hz @ 100kHz)。原型锁相环有效地为FMCW雷达应用产生快速(500MHz/55μs)和精确(824kHzrms频率误差)的三角啁啾。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2018 IEEE International Solid - State Circuits Conference - (ISSCC)

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