A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)

Abstract

A self-repairing fault-tolerant FPGA architecture is developed which is also compatible with existing island-style routing network. Due to this backward compatibility, the proposed architecture can not only be implemented easily in the existing FPGA devices but a new fault-tolerant FPGA device can also be fabricated utilizing the existing island-style routing architecture. A generic fault-tolerant Computation Cell is developed which can be incorporated in existing FPGA CLB (Configurable Logic Block) having 8 LUTs at least. The proposed fault-tolerant FPGA architecture is comprised of Computation Tiles each of which consists of computation cells which are able to heal themselves from transient errors. Computation Tile also contains stem cells which help computation cells to recover from permanent errors all at once. This architecture is centrally controlled by an on-chip fault-tolerant core whose main responsibility is to define the healing priority when an error occurs in more than one of the computation tile at the same time. It also communicates with the external PC software which identifies the faulty tile and reconfigures it through dynamic partial reconfiguration. The robust operation of a proposed architecture is implemented and verified on XILINX Virtex-5 FPGA device. From our proposed fault-tolerant scheme of utilizing the existing routing strategies together with partial reconfiguration of stem cells we achieved a number of benefits, including a fast fault recovery and avoidance of using complicated routing strategies, as compared to recently developed fault-tolerant FPGA architectures.