A 3×40Gb/s 28nm FDSOI CMOS front-end array with 10mVPP sensitivity and >4VPP output swing

Abstract

A versatile three-lane transceiver front-end is integrated in a production 28nm FDSOI CMOS technology. Each lane can operate at up to 40Gb/s data rate in receive mode with record 10mVPP sensitivity and 40dB gain, or up to 60Gb/s data rate in transmit mode with adjustable output swing between 2.6 and 4.3 VPP in a 50Ω load, as needed for a variety of silicon photonics and III-V optical modulators. The output stage can swing up to 100 mA at 60 Gb/s in 50Ω or 100fF capacitive loads. Single-ended CMOS inverter-based topologies are employed in all circuit blocks to minimize power consumption and to reduce the lane footprint to that of a ground-signal pad I/O. Even with the reduced footprint, special layout techniques enabled a lane-to-lane isolation better than 40 dB up to 55 GHz. The measured Tx-to-Rx dynamic range is larger than 54 dB at 40 Gb/s.