High performance double-gate device technology challenges and opportunities

Abstract

The double-gate FET is widely recognized as the prime candidate for the ultimate scaling of FETs to the shortest channel length. From the device integration point of view, the attainment of low extrinsic resistance, carrier transport in the double-gated thin silicon channel and threshold voltage control, remained significant obstacles to high-performance double-gate CMOS structures. We report how these issues were addressed to achieve world-record double-gate device performance. The second gate in a double-gate device can be utilized for low-power and mixed-signal applications. The flexibility of individually controlling the two gates provides opportunities for overall system performance improvement. Ultra-low voltage operation of double-gate CMOS inverters was demonstrated. Finally, we discuss the migration of existing circuit/layout designs to double-gate device technology.