Can spike timing dependent plasticity compensate for process mismatch in neuromorphic analogue VLSI?

Abstract

Analogue VLSI can be used to implement spike timing dependent neuromorphic training algorithms. This work presents a circuitry that uses spike timing to "adapt out" the effects of device mismatch in such circuits. Simulation results for the circuit implemented in 0.35 /spl mu/m CMOS process are reported.