Modular test generation and concurrent transparency-based test translation using gate-level ATPG

Abstract

We introduce a hierarchical test generation methodology for modular designs, employing exclusively gate-level ATPG. Based on the notion of modular transparency, the search space of the design is reduced to alleviate the complexity of gate-level test generation. Although ATPG is applied at the full circuit, faults in each module are targeted individually, while the surrounding modules are replaced by their much simpler, transparency-equivalent logic. As analyzed theoretically and as demonstrated through a set of experimental data, the proposed methodology results in significant test generation speed-up, while preserving comparable fault coverage and vector count to full-circuit gate-level ATPG.