250mV–950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS

Abstract

A 10K-gate 4Gbps unified encrypt/decrypt SMS4 Chinese cryptographic accelerator is fabricated in 14nm tri-gate CMOS, operating at 1GHz, 750mV, 25°C with total power consumption of 12mW. Double-affine mapped Sbox circuits enable inverse computation using GF(24)2 data-path, resulting in 33% reduction in accelerator area by elimination of look-up tables (LUT). Optimal composite-field reduction polynomials, counter-assisted round constant generation circuits, and a hybrid data-path with in-line key-expansion provide additional 14% area saving over traditional designs resulting in a compact layout occupying 2445μm2. Low voltage optimizations enable robust sub-threshold operation down to 250mV, with peak energy-efficiency of 1.1Tbps/W measured at 330mV.