A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI:10.1109/ISSCC42614.2022.9731614

Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, C. Cho, Sanghoon Kim, Donggun An, C. Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Young Park, Hyoung-Ju Kim, Ho-Seok Seol, Juhwan Kim, Junabum Shin, Kil Y. Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, ChanYong Lee, Seungseob Lee, T. Park, C. Oh, H. Ban, Hyungjong Ko, H. Song, T. Oh, Sang-Jun Hwang, Kyungseob Oh, J. Choi, Jooyoung Lee

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引用次数: 5

Abstract

Graphic DRAMs have been developed to increase maximum I/O interface speeds to satisfy the demand of high-performance graphic applications [1]–[5]. Recently, PAM4 signaling was utilized to increase the I/O bandwidth up to 22Gb/s/pin [5]. However, the reduced voltage margin of PAM4, compared to NRZ, complicates circuit design; margins also become worse with a reduced power supply. This paper achieves 27Gb/s in NRZ, a 1.5× speed enhancement, by improving on previous GDDR6 [3]. A T-coil is designed, for the first time in a DRAM process, so that the maximum operation frequency is increased. The proposed merged-MUX TX increases the maximum speed and reduces power and area consumption. A quad-skew training technique enables a wider clock sampling margin for WCK: up to 3ps, which is 8.1% of 1UI at 27Gbp/s/pin. Furthermore, a dual-mode frequency divider allows a wide-range operation from sub-1Gb/s/pin to 27Gb/s/pin. An alternative-data-bus (ADB) is proposed to solve the frequency limit of the data bus.

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一种16Gb、27Gb/s/引脚t圈型GDDR6 DRAM，具有合并mux TX、优化WCK操作和备选数据总线

图形dram的发展是为了提高最大I/O接口速度，以满足高性能图形应用的需求[1]-[5]。最近，PAM4信令被用于将I/O带宽提高到22Gb/s/pin[5]。然而，与NRZ相比，PAM4的电压裕度降低，使电路设计复杂化;随着电力供应的减少，利润率也会变得更糟。本文通过对前人GDDR6[3]的改进，在NRZ中实现了27Gb/s，速度提升了1.5倍。在DRAM工艺中首次设计了t型线圈，从而提高了最大工作频率。所提出的合并mux TX提高了最大速度，降低了功耗和面积消耗。四斜训练技术可以为WCK提供更宽的时钟采样裕度:高达3ps，在27Gbp/s/引脚时为1UI的8.1%。此外，双模分频器允许从低于1gb /s/引脚到27Gb/s/引脚的宽范围工作。为了解决数据总线的频率限制问题，提出了一种替代数据总线(ADB)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 IEEE International Solid- State Circuits Conference (ISSCC)

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