The Parasitic Capacitance Effect Calibration Scheme of The Split Structure SAR ADC

Abstract

In this paper, a parasitic capacitance calibration scheme of split structure SAR ADC based on redundant bridged capacitor is proposed. A digitally controlled compensation capacitor array is used for parasitic capacitor calibration. By the comparison of the MSB-side last-bit capacitor and all the capacitors in LSB-side, the calibration capacitor array is employed to compensate the weight error caused by the parasitic capacitor. Compared with other similar calibration techniques, this calibration scheme is suitable for top-plate sampling architecture. The prototype is implemented in 40nm CMOS technology, the core area is 350um*250um. After calibration, an SNDR of 68.85dB and an SFDR of 83.11dB are achieved with the with the Nyquist rate input at a sampling rate of 160MS/s, consuming the core power of 2.1mW at 1.1V supply voltage.