A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of −246dB for IoT applications in 65nm CMOS

Abstract

In a world that has become increasingly connected by the Internet, ultra-low-power (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF pLl in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Compared with the analog PLLs, an ADPLL is more advantageous in nm-CMOS technologies [1-6]. This paper presents a 2.0-to-2.8GHz 653μW fractional-N ADPLL that achieves −242dB FOM in 65nm CMOS for 2.4GHz ISM band applications. The best power-jitter trade-off is achieved at 981μW using a reference doubler with 535fs jitter and a −56dBc in-band fractional spur, which corresponds to a FOM of −246dB. Thanks to the proposed 10b isolated constant-slope DTC, this ADPLL breaks the −240dB FOM barrier of sub-mW fractional-N ADPLLs.