Design and implementation of FFT pruning algorithm on FPGA

Abstract

Digital Signal Processing (DSP) has evolved as an integrated component in electronics advancement. Among all the DSP operations, Fast Fourier Transform (FFT) plays a prominent role in signal processing. FFT computational time reduces when the number of zero valued inputs (Z) outnumbers the non-zero valued inputs (NZ) due to unnecessary computations for Z. The above issue can be resolved by minimizing computations on Ζ by the method Pruning (Partial, Complete) in FFT. The pruning method is implemented in the hardware and computational time improvement is observed. The FFT Pruning is developed in Verilog and validated on Spartan 3E FPGA (xc3s500e-fg320-5).