Analog front-end and power management integration on a 0.13 /spl mu/m CMOS ADSL SoC

Abstract

This paper describes the analog and power management aspects of a single chip asymmetric digital subscriber line (ADSL) customer premises equipment (CPE) router. We address the system partitioning between analog and digital resulting in optimum system cost and performance for a .13 /spl mu/m CMOS process.