First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration

Abstract

Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area panel-scalable glass substrate processes with lower cost, 2) silicon-like RDL on large panels with 1-2 µm critical dimensions (CD), 3) lower interconnect loss and 4) improved board-level reliability enabled by the tailorability of the CTE of the glass panels and compliant interconnections. Daisy-chain test dies were used to emulate an embedded device with the size of 6.469 mm × 5.902 mm, thickness of 75 µm and pad pitch of 65 µm. Glass panels with 70 µm thickness and through-glass cavities were first fabricated, and then bonded onto a 50 µm thick glass panel carrier using adhesives. After glass-to-glass bonding, the test dies were assembled into the glass cavities using a high-speed placement tool. RDL polymers were then laminated onto both sides and cured to minimize the warpage of the ultra-thin package. A surface planar tool was then used to planarize the surface of the panel to expose the copper microbumps on the die, followed by a standard semi-additive process (SAP) for the fan-out RDL layer. The shift and warpage of the die were characterized during the multiple process steps. Initial modeling and measured results indicate the potential for less than 5 µm die shift and less than 10-15 µm warpage across a 300 mm × 300 mm panel size.