A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573465

A. Sanyal, Nan Sun

引用次数: 25

Abstract

A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.

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18.5 fj /step VCO-based 0-1 MASH ΔΣ数字背景校准ADC

本文提出了一种缩放友好且节能的0-1 MASH ΔΣ ADC。使用8b SAR作为粗量化的第一阶段。环形压控振荡器作为第二级进行精细量化。所提出的ADC使用数字背景校准来跟踪VCO在pvt中的增益变化。在1.1V电源下，40nm CMOS原型实现了18.5 fJ/ v-step的Walden FoM。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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