Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

Abstract

Many-core processors with on-die network-on-chip (NoC) interconnects have emerged as viable architectures for Single-Instruction/Multiple-Data (SIMD) vector applications and parallel workloads, and have been implemented in 65nm CMOS with Dynamic Voltage-Frequency Scaling (DVFS). Chips with Single-Voltage/Single-Frequency (SVSF) for all cores running homogeneous threads as well as Multiple-Voltage/Multiple-Frequency (MVMF), running heterogeneous applications and using independent V/F control for each core, have been reported. Combination of DVFS with dynamic core-count scaling (or DVFCS) has been proposed to further improve performance & energy efficiency across varying workloads. With technology scaling, both leakage power and core-to-core variations in frequency (Fmax) & leakage due to within-die device parameter variations have become significant, thus creating the need for per-core power gating and variation-aware DVFCS. Recently, variation-aware core mapping has been investigated using high level architectural simulations and statistical variation models.