Session 25 Overview: DRAM Memory Subcommittee

Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim
{"title":"Session 25 Overview: DRAM Memory Subcommittee","authors":"Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim","doi":"10.1109/ISSCC42613.2021.9365948","DOIUrl":null,"url":null,"abstract":"First devices for the new DRAM standards LPDDR5 and DDR5 are implementing improvements in bandwidth and power efficiency. The new devices will have a huge impact on a very wide range of applications, from IoT applications and smartphones to server and workstation applications. A new proposal for managed LRDIMM promises to reduce cost and power, and to provide capacities up to 512GB. For next generation DRAM interfaces a PAM-3 transceiver with 27Gb/s/pin on the base of 3 bits per 2 symbols is presented. -generation LPDDR5 the maximum bandwidth as WCK clocking and non-target ODT (NT-ODT). power consumption using techniques such as dynamic voltage frequency scaling (DVFS), and a deep-sleep mode (DSM). presents a DDR5 SDRAM to overcome bandwidth, power and capacity limitations of DDR4. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a phase-rotator-based DLL, write-level training, and RX/TX with the enhanced DFE/FFE. The energy efficiency is improved by more than 30% with 1.1V/1.8V VDD and VPP. a 3bit/2UI 1.03pJ/bit PAM-3 single-ended TRX. An 27Gb/s PAM-3 symbol is generated with an output driver voltage of 0.6V and a 1/3-rate forwarded clock frequency of 9GHz. The RX adopts a 1-tap tri-level DFE, which has the same complexity as for NRZ signaling to equalize the PAM-3 signal. Fabricated in a 28nm CMOS technology, the proposed PAM-3 TRX can be utilized for the next generation memory interface with low power. (ODP) structured (media) and ODP structure of for cost minimization, pre-CMD scheme for reduction. Dies per wafer increase of compared to conventional DRAM with same process and same capacity was achieved. DIMM power consumption is","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"26 1","pages":"342-343"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9365948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

First devices for the new DRAM standards LPDDR5 and DDR5 are implementing improvements in bandwidth and power efficiency. The new devices will have a huge impact on a very wide range of applications, from IoT applications and smartphones to server and workstation applications. A new proposal for managed LRDIMM promises to reduce cost and power, and to provide capacities up to 512GB. For next generation DRAM interfaces a PAM-3 transceiver with 27Gb/s/pin on the base of 3 bits per 2 symbols is presented. -generation LPDDR5 the maximum bandwidth as WCK clocking and non-target ODT (NT-ODT). power consumption using techniques such as dynamic voltage frequency scaling (DVFS), and a deep-sleep mode (DSM). presents a DDR5 SDRAM to overcome bandwidth, power and capacity limitations of DDR4. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a phase-rotator-based DLL, write-level training, and RX/TX with the enhanced DFE/FFE. The energy efficiency is improved by more than 30% with 1.1V/1.8V VDD and VPP. a 3bit/2UI 1.03pJ/bit PAM-3 single-ended TRX. An 27Gb/s PAM-3 symbol is generated with an output driver voltage of 0.6V and a 1/3-rate forwarded clock frequency of 9GHz. The RX adopts a 1-tap tri-level DFE, which has the same complexity as for NRZ signaling to equalize the PAM-3 signal. Fabricated in a 28nm CMOS technology, the proposed PAM-3 TRX can be utilized for the next generation memory interface with low power. (ODP) structured (media) and ODP structure of for cost minimization, pre-CMD scheme for reduction. Dies per wafer increase of compared to conventional DRAM with same process and same capacity was achieved. DIMM power consumption is
会议25概述:DRAM内存小组委员会
首批采用新DRAM标准LPDDR5和DDR5的设备正在实现带宽和功率效率方面的改进。这些新设备将对广泛的应用产生巨大影响,从物联网应用和智能手机到服务器和工作站应用。一项关于管理LRDIMM的新提议承诺降低成本和功耗,并提供高达512GB的容量。对于下一代DRAM接口,提出了一种基于每2个符号3比特的27Gb/s/引脚的PAM-3收发器。LPDDR5的最大带宽作为WCK时钟和非目标ODT (NT-ODT)。使用动态电压频率缩放(DVFS)和深度睡眠模式(DSM)等技术来降低功耗。提出了一种克服DDR4带宽、功率和容量限制的DDR5 SDRAM。本文提出了一个16Gb 6.4Gb/s/引脚的DDR5 SDRAM,具有基于相位旋转器的DLL,写级训练和RX/TX,具有增强的DFE/FFE。采用1.1V/1.8V VDD和VPP,能效提高30%以上。一个3bit/2UI 1.03pJ/bit PAM-3单端TRX。生成一个27Gb/s的PAM-3符号,输出驱动电压为0.6V, 1/3速率转发时钟频率为9GHz。RX采用1分接三电平DFE,其复杂度与NRZ信令相同,用于均衡PAM-3信号。PAM-3 TRX采用28nm CMOS工艺制造,可用于下一代低功耗存储器接口。(ODP)结构(介质)和ODP结构的成本最小化,预cmd方案的减少。与传统DRAM相比,在相同工艺和相同容量的情况下,每片芯片的芯片数增加了。DIMM功耗为
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信