Channel-width dependent hot-carrier degradation of thin-gate pMOSFETs

Abstract

Channel width dependent pMOSFET hot-carrier degradation has been observed for a 0.25 /spl mu/m CMOS technology. A detailed characterization revealed two distinct trapping mechanisms that are unique to both narrow and wide width devices. Device simulations indicate that the electric field difference between the STI edge and channel area is responsible for the channel-width dependent degradation. In addition to data from discrete devices, product burn-in data will also be presented to support the channel-width dependent pMOST degradation mechanism.