Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits

H. Fuketa, M. Nomura, M. Takamiya, T. Sakurai
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引用次数: 12

Abstract

In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum. Resonant clocking can reduce the effective capacitance of the clock distribution network. In this work, a new resonant clocking scheme enabling power reduction at any clock frequency is proposed and applied to a 0.37V 980kHz near-Vt logic circuit in 40nm CMOS.
间歇谐振时钟使功率降低在任何时钟频率0.37V 980kHz近阈值逻辑电路
为了提高逻辑电路的能量效率,需要降低电容(C)和电源电压(VDD),因为能量消耗与CVDD2成正比。近阈值(Vt)操作达到能量最小。谐振时钟可以降低时钟配电网的有效电容。在这项工作中,提出了一种新的谐振时钟方案,可以在任何时钟频率下降低功率,并应用于40nm CMOS的0.37V 980kHz近vt逻辑电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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