Effects of parasitic capacitances on gallium nitride heterostructure power transistors

Abstract

The parasitic capacitances of GaN have been evaluated in order to assess the impact that each capacitance has on the switching losses of GaN devices. This required developing and validating equivalent GaN HFET device models in SaberRD and implementing the models in a switching test circuit under variable parasitic capacitance conditions. The data presented here can facilitate optimizing the area and hence capacitance of GaN devices for future generation power electronics.