7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor

Abstract

The L1 cache for the 5.5 GHz 32nm zEnterprise™ EC12 processor requires SRAM designs that make aggressive use of dynamic circuitry. As technology has scaled and transistor counts have grown, random device variability [1] and power limitations have become significant challenges. In particular, random device-variability-induced pulse shrinkage and misalignment in dynamic signals must be carefully addressed. Described here are a series of new design approaches enabling L1 cache SRAM operation at 7GHz, including a 3-level bitline hierarchy, decreased dynamic path lengths, localized read enables, and a power-savings mechanism in which selective columns can be partially powered down.