Cost-effective rasterization using valid screen space region

Abstract

Due to the progress of consumer electronics, 3D-Graphics system has become mobilizing and attractive. In order to render 3D graphic in efficiency, the rasterization techniques are developed. Traditional clipping techniques using the six-planes of view volume to split outside part of primitive are complicated and not cost-effective. For 3D graphics gaming application with high resolution in mobile device, the cost-effective hardware is crucial and necessary. This paper proposes a novel cost-effective strategy for primitives clipping in rasterization. In the entire process, no expensive clipping action is involved and no extra clipping-derived polygons are produced. The proposed architecture which processes the valid screen space region of each primitive in 8 cycles and the gate-count is 20k only, using the TSMC 65nm 1P9M process and the throughput reach 25 M Triangles/Sec.