{"title":"A Sigma-Delta ADC with Complementary T-Switch","authors":"Yisu Guo, Jing Jin, Haoyu Liu, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660298","DOIUrl":null,"url":null,"abstract":"This paper presents a sigma-delta ADC applied to precision temperature sensors, which using the VPTAT generated by the front-end circuit as the input VREF to read the temperature digitally. A T-switch design with complementary structure is used in the sample-holding circuit, which greatly reduces the number of switches and decreases the distortion caused by charge injection effect and leakage current. This circuit is designed in TSMC 0.18μm CMOS processes. The simulation results show that the static power consumption of the circuit is 6S.S3μW (@27°C) under the supply voltage of 1.SV. In the range of -45°C~85°C, the signal-to-noise and distortion ratio (SNDR) is 89. 2dB, the effective number of bits (ENOB) is 14. 53bits, the oversampling rate (OSR) is 512. The core area of the circuit is 224.4μm× 248.76μm.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"4 1","pages":"380-383"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM54364.2021.9660298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a sigma-delta ADC applied to precision temperature sensors, which using the VPTAT generated by the front-end circuit as the input VREF to read the temperature digitally. A T-switch design with complementary structure is used in the sample-holding circuit, which greatly reduces the number of switches and decreases the distortion caused by charge injection effect and leakage current. This circuit is designed in TSMC 0.18μm CMOS processes. The simulation results show that the static power consumption of the circuit is 6S.S3μW (@27°C) under the supply voltage of 1.SV. In the range of -45°C~85°C, the signal-to-noise and distortion ratio (SNDR) is 89. 2dB, the effective number of bits (ENOB) is 14. 53bits, the oversampling rate (OSR) is 512. The core area of the circuit is 224.4μm× 248.76μm.