{"title":"A parallel technique for M-D digital signal processing","authors":"M.B.E. Abdelrazik","doi":"10.1109/MWSCAS.1991.252019","DOIUrl":null,"url":null,"abstract":"The authors describe a parallel technique for decomposition and implementation of multidimensional linear time invariant systems. The resulting structures are regular, modular, and highly parallel. The approach used is systematic, and therefore it would be useful for logic synthesis. The application of such an approach in digital signal processing (DSP) and numerical computations reduces the design time, resulting in low cost. This approach produces various structures (semi-systolic, quasi-systolic, and pure systolic structures) which could be considered as application specific array processors.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"14 1","pages":"688-691 vol.2"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.1991.252019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The authors describe a parallel technique for decomposition and implementation of multidimensional linear time invariant systems. The resulting structures are regular, modular, and highly parallel. The approach used is systematic, and therefore it would be useful for logic synthesis. The application of such an approach in digital signal processing (DSP) and numerical computations reduces the design time, resulting in low cost. This approach produces various structures (semi-systolic, quasi-systolic, and pure systolic structures) which could be considered as application specific array processors.<>