A Multi-Layered Air-Gap Transmission Line Design for CMOS-Compatible Millimeter-Wave ICs

Abstract

A compact and chip-area efficient transmission line design is proposed for monolithic millimeter-wave integrated circuits. Performance improvement is achieved by the use of multi-layered air-gaps compatible to CMOS fabrication. Based on a 65-nm CMOS process, the on-chip transmission line occupies less than 17 μm in width and 8 μm in height while active devices and circuits can still be fabricated with interconnect routing right beneath the shielded structure of the transmission line. The semi-enclosed structure allows the tuning of the characteristic impedance. 3D electromagnetic simulations give results of 1.8 dB/mm insertion loss and a reflection coefficient of −28 dB at 60 GHz, for a 50-ohm matched design. The multi-layered air-gap design allows the current density more uniformly distributed in the signal-carrying conductor compared with a counterpart design without air-gaps.