FPGA-based hardware-in-the-loop verification of dual-stage HDD head position control

Abstract

This paper presents a design and verification of a digital controller for dual-stage hard disk drive (HDD) head positioning. A continuous time model of an adaptive PID controller of the dual-stage track following control is converted to a stable discrete time model. Then, the optimizations of sampling rate, arithmetic operation bit-width, and control parameters are performed during digital controller design. Xilinx System Generator is used to generate the hardware description language that can be implemented in a real FPGA. Finally, hardware-in-the-loop verification is performed through a hardware board to guarantee the control model. This method can not only accelerate the design cycle of new HDD models, but also achieve high sampling rate precise head position control implementations. From the verification results, our proposed controller can work at 5.64 MHz sampling rate on a low cost FPGA (Xilinx Spartan-III XC3S400) and the position error (3-sigma) is only 4.2138 % of track.