A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time

Abstract

At the center of autonomous driving and range and motion sensing in industrial and healthcare applications are FMCW RADARs, which provide the means for object range and velocity estimation. With future widespread use and availability of more bandwidth for RADAR systems, FMCW generators with short chirp duration and low phase noise will be important to reduce the RADAR doppler-induced range ambiguity and improve its resolution of close targets in multi-target environments. Due to the conflicting tradeoffs between bandwidth and low phase noise, PLLs with two-point modulation (TPM) are commonly used. The TPM architecture suffers from 2 main drawbacks: 1) In analog implementations [1, 2], it requires a low-noise DAC to inject a modulation signal in the sensitive tuning port of the VCO degrading phase noise, 2) Due to the finite matching between the high- and low-pass paths of the PLL, it introduces FM errors, which degrade the linearity of the generated chirps and require calibration. This is true for analog and digital implementations [3]. This work presents a FMCW modulator using an RTWO-based ADPLL to alleviate the phase-noise-versus-settling-time limitations of conventional PLL architectures. It generates sawtooth chirps with slopes up to 65MHz/μs, 2μs settling time, 12.5ns chirp retrace time, and 37kHz rms FM error. This is while achieving phase noise of -120dBc/Hz at a 1MHz offset from a 10GHz RF carrier.