A new CAM macro for 622 Mbps ATM cell processing

H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai
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引用次数: 1

Abstract

A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.
用于622 Mbps ATM单元处理的新CAM宏
开发了一种用于622 Mbps ATM单元处理的CAM宏,该宏内置两个电路:空闲字检测电路和多命中检测电路。该宏采用标准的0.5 /spl mu/m 3层CMOS技术制造,工作频率为40 MHz,功耗为70 mW,电源为3.3 V。
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CiteScore
3.80
自引率
0.00%
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0
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