System and Technology Co-optimization for RRAM based Computation-in-memory Chip

Abstract

In order to improve accuracy and robustness of RRAM based computation-in-memory chip, device-circuit-algorithm co-optimization with consideration of underlying device and array nonidealities should outperform the individual optimization of device or algorithm. In this work, we provide a device-circuit-algorithm simulation framework and propose the corresponding design guidelines. The simulation framework supports both inference and on-chip training, and a physics-based device model for analog RRAM is embedded to the framework to benchmark the CIM system. Nonideal effects and reliability issues of analog RRAM device are fully considered. Besides, array IR-drop and peripheral circuit are also modeled. Based on the evaluation results, optimization guidelines to suppress the impact of device nonidealities, reliability degradation and array IR-drop are proposed. This work provides a useful end-to-end co-design tool for developing large-scale computation-in-memory systems.