Non-intrusive bit swapping pattern generator for BIST testing of LUTs

Abstract

This paper presents the non-intrusive built-in self-test system (BIST) for the test pattern generator (TPG) and output response analyzer (ORA) for testing of the field programmable gate array (FPGA). It consists of software and hardware parts with channels in between them to establish communication. The test generation and the response analysis are done in the software part whereas the hardware part is the circuit under test. Another FPGA is used to perform the interfacing operation. The configuration numbers are greatly reduced in this technique when compared with the embedded BIST technique. By incorporating bit-swapping linear feedback shift register (BS-LFSR) as the TPG instead of the conventional LFSR, transition numbers are reduced effectively. Hence the overall switching activity is reduced during the test operation, minimizing the power.