The design of a high gain on-chip antenna for SoC application

Abstract

A V-band high gain and high efficiency on-chip antenna in a CMOS 0.18-μm process is presented in this work. High resistivity silicon substrate, dielectric resonator and a layer of off-chip ground are used in this design to enhance the antenna gain and reduce the antenna size. The proposed antenna achieves a maximum gain of 8 dBi with a -10 dB bandwidth of 4 GHz. The peak antenna efficiency is 96.7% and the half-power-beamwidth is 72° and 92° in the E-and H-plane respectively. Moreover, the chip size of the presented antenna is 700 μm × 1250 μm.