CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique

M. S. Haque, Jorgen Peddersen, S. Parameswaran
{"title":"CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique","authors":"M. S. Haque, Jorgen Peddersen, S. Parameswaran","doi":"10.1109/ICCAD.2011.6105316","DOIUrl":null,"url":null,"abstract":"An application's cache miss rate is used in timing analysis, system performance prediction and in deciding the best cache memory for an embedded system to meet tighter constraints. Single-pass simulation allows a designer to find the number of cache misses quickly and accurately on various cache memories. Such single-pass simulation systems have previously relied heavily on cache inclusion properties, which allowed rapid simulation of cache configurations for different applications. Thus far the only inclusion properties discovered were applicable to the Least Recently Used (LRU) replacement policy based caches. However, LRU based caches are rarely implemented in real life due to their circuit complexity at larger cache associativities. Embedded processors typically use a FIFO replacement policy in their caches instead, for which there are no full inclusion properties to exploit. In this paper, for the first time, we introduce a cache property called the “Intersection Property” that helps to reduce single-pass simulation time in a manner similar to inclusion property. An intersection property defines conditions that if met, prove a particular element exists in larger caches, thus avoiding further search time. We have discussed three such intersection properties for caches using the FIFO replacement policy in this paper. A rapid single-pass FIFO cache simulator “CIPARSim” has also been proposed. CIPARSim is the first single-pass simulator dependent on the FIFO cache properties to reduce simulation time significantly. CIPARSim's simulation time was up to 5 times faster (on average 3 times faster) compared to the state of the art single-pass FIFO cache simulator for the cache configurations tested. CIPARSim produces the cache hit and miss rates of an application accurately on various cache configurations. During simulation, CIPARSim's intersection properties alone predict up to 90% (on average 65%) of the total hits, reducing simulation time immensely.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"21 1","pages":"126-133"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.2011.6105316","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

An application's cache miss rate is used in timing analysis, system performance prediction and in deciding the best cache memory for an embedded system to meet tighter constraints. Single-pass simulation allows a designer to find the number of cache misses quickly and accurately on various cache memories. Such single-pass simulation systems have previously relied heavily on cache inclusion properties, which allowed rapid simulation of cache configurations for different applications. Thus far the only inclusion properties discovered were applicable to the Least Recently Used (LRU) replacement policy based caches. However, LRU based caches are rarely implemented in real life due to their circuit complexity at larger cache associativities. Embedded processors typically use a FIFO replacement policy in their caches instead, for which there are no full inclusion properties to exploit. In this paper, for the first time, we introduce a cache property called the “Intersection Property” that helps to reduce single-pass simulation time in a manner similar to inclusion property. An intersection property defines conditions that if met, prove a particular element exists in larger caches, thus avoiding further search time. We have discussed three such intersection properties for caches using the FIFO replacement policy in this paper. A rapid single-pass FIFO cache simulator “CIPARSim” has also been proposed. CIPARSim is the first single-pass simulator dependent on the FIFO cache properties to reduce simulation time significantly. CIPARSim's simulation time was up to 5 times faster (on average 3 times faster) compared to the state of the art single-pass FIFO cache simulator for the cache configurations tested. CIPARSim produces the cache hit and miss rates of an application accurately on various cache configurations. During simulation, CIPARSim's intersection properties alone predict up to 90% (on average 65%) of the total hits, reducing simulation time immensely.
缓存交集属性辅助快速单次FIFO缓存仿真技术
应用程序的缓存缺失率用于时间分析,系统性能预测以及为嵌入式系统决定最佳缓存内存以满足更严格的约束。单次模拟允许设计人员在各种缓存存储器上快速准确地找到缓存丢失的数量。这种单遍模拟系统以前严重依赖于缓存包含属性,这允许快速模拟不同应用的缓存配置。到目前为止,发现的唯一包含属性适用于基于最近最少使用(Least Recently Used, LRU)替换策略的缓存。然而,基于LRU的缓存在现实生活中很少实现,因为它们在较大的缓存关联下的电路复杂性。嵌入式处理器通常在其缓存中使用FIFO替换策略,因此没有完整的包含属性可以利用。在本文中,我们首次引入了一种称为“交集属性”的缓存属性,它有助于以类似于包含属性的方式减少单次通过的模拟时间。交集属性定义了一些条件,如果满足这些条件,就证明某个特定元素存在于较大的缓存中,从而避免进一步的搜索时间。我们在本文中讨论了使用FIFO替换策略的缓存的三个这样的交集属性。提出了一种快速单次FIFO缓存模拟器“CIPARSim”。CIPARSim是第一个依赖于FIFO缓存属性的单遍模拟器,可以显着减少模拟时间。对于所测试的缓存配置,CIPARSim的模拟时间比最先进的单通道FIFO缓存模拟器快5倍(平均快3倍)。CIPARSim可以在不同的缓存配置下准确地生成应用程序的缓存命中率和未命中率。在模拟过程中,仅CIPARSim的交叉属性就可以预测高达90%(平均65%)的总命中,极大地减少了模拟时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信