{"title":"A 78.8–92.8 GHz 4-bit 0–360° active phase shifter in 28nm FDSOI CMOS with 2.3 dB average peak gain","authors":"D. Pepe, D. Zito","doi":"10.1109/ESSCIRC.2015.7313829","DOIUrl":null,"url":null,"abstract":"A 78.8-92.8 GHz 4-bit (16 phases) digitally controlled vector modulator active phase shifter has been designed and implemented in 28nm FDSOI CMOS by STMicroelectronics. The phase shifter exploits a novel IQ generator based on a cascode amplifier incorporating a lumped element coupled line quadrature coupler to generate the in-phase (I) and quadrature (Q) signals. The phase shifter consumes 18 mA from a 1.2 V supply. The measured performances are: average gain of 2.3 dB at 87.4 GHz (between 3.2 and -1.6 dB for the 16 phase states) and -3 dB bandwidth (B3dB) from 78.8 to 92.8 GHz; RMS gain error equal to 1.68 dB at 87.4 GHz and lower than 2 dB in the B3dB; RMS phase error equal to 9.4o at 87.4 GHz and lower than 11.9o in the B3dB; S11 lower than -10.5 dB in the B3dB; average input referred 1 dB compression point of -7 dBm (between -8 and -5 dBm for the 16 phase states); average noise figure equal to 10.8 dB at 87 GHz (between -9 and -12 dB for the 16 phase states).","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":"23 1","pages":"64-67"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313829","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
Abstract
A 78.8-92.8 GHz 4-bit (16 phases) digitally controlled vector modulator active phase shifter has been designed and implemented in 28nm FDSOI CMOS by STMicroelectronics. The phase shifter exploits a novel IQ generator based on a cascode amplifier incorporating a lumped element coupled line quadrature coupler to generate the in-phase (I) and quadrature (Q) signals. The phase shifter consumes 18 mA from a 1.2 V supply. The measured performances are: average gain of 2.3 dB at 87.4 GHz (between 3.2 and -1.6 dB for the 16 phase states) and -3 dB bandwidth (B3dB) from 78.8 to 92.8 GHz; RMS gain error equal to 1.68 dB at 87.4 GHz and lower than 2 dB in the B3dB; RMS phase error equal to 9.4o at 87.4 GHz and lower than 11.9o in the B3dB; S11 lower than -10.5 dB in the B3dB; average input referred 1 dB compression point of -7 dBm (between -8 and -5 dBm for the 16 phase states); average noise figure equal to 10.8 dB at 87 GHz (between -9 and -12 dB for the 16 phase states).