An align-insensitive through-wafer-via for wafer-stacked structure

Abstract

An interconnection scheme which has the merits of align-insensitivity and wafer bonding compatibility is suggested for wafer stacked structure with the silicon through-wafer-via. The interconnection structures in the previous works using a prominent copper solder and metal reflow technique have alignment problems when wafers are bonded for stacking. The suggested modified interconnection scheme prevents from alignment problems by improving prominent copper solder structure and filling method of trench isolation in thorugh-wafer-via. The suggested interconnection structure is fabricated to show feasibility and mechanical wafer warpage is investigated.